GATE2003 q78 79 - Revision history

Arjun Suresh at 20:00, 30 January 2015

2015-01-30T20:00:22Z

2014-07-15T11:32:08Z

2014-07-15T11:30:19Z

2014-07-13T22:47:11Z

2014-04-15T07:07:39Z

2014-04-14T14:00:12Z

2014-02-27T22:18:08Z

2014-02-27T22:14:50Z

‎Solution

2014-02-27T22:14:28Z

‎Solution

2014-02-27T22:13:56Z

‎Solution

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 ==={{Template:Author|Arjun Suresh|{{arjunweb}} }}===
-. It's given cache is physically addressed. So, address translation is needed for all memory accesses.
+. It is given cache is physically addressed. So, address translation is needed for all memory accesses.
   Average access time = Average address translation time + Average memory access time
   = 1ns (TLB is accessed for all accesses) + 2*10*0.04 (2 page tables accessed from main memory in case of TLB miss) + Average memory access time

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 [[Category: GATE2003]]
 [[Category: OS questions from GATE]]
-[[Category: Architecture questions GATE]]
+[[Category: Architecture questions from GATE]]

@@ Line 44: / Line 44: @@
 [[Category: GATE2003]]
-[[Category: OS questions]]
+[[Category: OS questions from GATE]]
-[[Category: Architecture questions]]
+[[Category: Architecture questions GATE]]

@@ Line 43: / Line 43: @@
 [[Category: GATE2003]]
 [[Category: OS questions]]
 [[Category: Architecture questions]]

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 [[Category: Operating Systems]]
 [[Category: GATE2003]]
-[[Category: Previous year GATE questions]]
+[[Category: OS questions]]

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 (A) 8 KB (B) 12 KB '''(C) 16 KB''' (D) 20 KB
-===Solution ===
+==={{Template:Author|Arjun Suresh|{{arjunweb}} }}===
 . It's given cache is physically addressed. So, address translation is needed for all memory accesses.

@@ Line 19: / Line 19: @@
 . Suppose a process has only the following pages in its virtual address space: two
 contiguous code pages starting at virtual address 0x00000000, two contiguous
-data pages starting at virtual address 0×00400000, and a stack page starting at
+data pages starting at virtual address 0x00400000, and a stack page starting at
 virtual address 0xFFFFF000. The amount of memory required for storing the page
 tables of this process is
@@ Line 36: / Line 36: @@
-. First level page table is addressed using 10 bits and hence contains <math>2^{10}</math> entries. Each entry is 4 bytes and hence this table requires 4 KB. Now, the process uses only 3 unique entries from this 1024 possible entries. Hence there are only 3 second level page tables. Each of these second level page tables are also addressed using 10 bits and hence of size 4 KB. So, total page table size of the process
+. First level page table is addressed using 10 bits and hence contains <math>2^{10}</math> entries. Each entry is 4 bytes and hence this table requires 4 KB. Now, the process uses only 3 unique entries from this 1024 possible entries (two code pages starting from 0x00000000  and two data pages starting from 0x00400000 have same first 10 bits). Hence, there are only 3 second level page tables. Each of these second level page tables are also addressed using 10 bits and hence of size 4 KB. So,
   = 4 KB + 3 * 4 KB
   = 16 KB